1. Field of the Invention
The present invention relates to semiconductor device manufacturing, and more particularly to a method that controllably forms in-situ notched gate structures.
2. Background of the Invention
In the semiconductor industry, complementary metal oxide semiconductor (CMOS) devices such as metal oxide semiconductor field effect transistors (MOSFETs) are consistently required to be made smaller and smaller to meet expected performance improvements. An important size measurement of such transistors is the gate length. As the gate length decreases, other portions of the device must correspondingly decrease in size to match the size (e.g., to scale in size) of the gate length. It is also desirable to reduce the gate length more aggressively than can be achieved using the highest level of available lithography. Typically, MOSFETs having a sub 0.05 micron electrical critical dimension are presently desirable.
One advance that allows the gate length of a MOSFET to be reduced beyond the smallest feature size available in current lithography is to notch the bottom portion of the gate conductor material, e.g., polysilicon. Notched gates reduce the gate length dimension at the gate conductor/gate dielectric interface thereby improving device performance, yet the notched gates do not require the remainder of the device to suffer a similar reduction in scale. However, notching of the lower portion of the gate with prior art processes is problematic in several cases.
FIG. 1 illustrates a typical prior art notched gate structure. Specifically, the structure shown in FIG. 1 comprises semiconductor substrate 10, a layer of gate dielectric 12 formed on a surface of semiconductor substrate 10, and patterned notched gate region 14 formed on a portion on gate dielectric 12. The patterned notched gate region includes gate material 16 having notches 18 formed in a lower portion thereof and dielectric mask 20 formed atop gate material 16. In the present case, gate material 16 is comprised of polysilicon.
The notching at the base of the gate material shown in FIG. 1 depends strongly on the 10 combination of: (i) the charging of both dielectric mask 20 and gate dielectric 12, (ii) the anisotropic, i.e., ion-driven, etching agent, and (iii) the high sputter yield of the polysilicon gate material. More specifically, incoming ions (labeled as 22 in FIG. 1) curve towards the base of gate material 16 to create notches 18. Ions 22 are deflected by the static charge on dielectric mask 20 which has a negative charge due to thermal electron distribution. In addition, gate dielectric 12 has a positive charge due to anisotropic ion distribution, which attracts deflected ions back toward the lower corners of gate material 16. This selective charging leads to both a high sputter yield of silicon as well as removal of the sidewall passivant, allowing chlorine radicals to attack gate material 16 and create notches 18.
However, with such processing, the notch profile is uncontrollable and depends strongly on the relative charging of both dielectric mask 20 and gate dielectric 12, the incoming ion flux 22, the radical flux at the base, the doping level of the polysilicon gate material, as well as several other factors. It is impossible to simultaneously control all of these factors in current plasma based etching systems, and hence formation of notch 18 by this mechanism can lead to an unacceptably wide variation in device performance.
In view of the drawbacks mentioned hereinabove, there is a continued need for providing a new and improved method of forming a notched gate structure that is more reliable than the current state of the art.
One object of the present invention is to provide a MOSFET device in which the gate region has feature sizes that are below those that can be obtained from conventional lithography, i.e., sub 0.05 micron electrical critical dimension.
A further object of the present invention is to provide a method of controllably forming a notched gate structure which avoids the drawbacks that are associated with prior art processes of fabricating notched gate structures.
A yet further object of the present invention is to provide a method of fabricating a notched gate structure which utilizes processing steps that are compatible with existing CMOS processing steps.
A still further object of the present invention is to provide a method of fabricating a notched gate structure in which the gate electrical critical dimension (CD) is substantially reduced so as to improve the performance of the device.
An even further object of the present invention is to provide a method of fabricating a notched gate structure in which the total gate capacitance, as determined by the contact length of the gate across the gate dielectric, is reduced below values that can be obtained using current lithographic processes. In particular, it is desired to reduce the gate length more aggressively than the scale of the available gate structures (determined by available lithography).
These and other objects and advantages are achieved in the present invention by utilizing a unique, controllable, in-situ method of defining a notched gate region wherein a C-containing and/or Si-containing passivating film is employed to protect portions of the gate region during notch formation. The inventive method additionally affords cost and performance improvements over existing prior art processes for notching a gate.
Specifically, the method of the present invention, which is employed in controllably forming an in-situ notched gate structure, comprises the steps of:
(a) forming a gate conductor layer having a first thickness on a surface of a gate dielectric;
(b) forming a patterned mask over a portion of said gate conductor layer;
(c) etching said gate conductor layer in regions not protected by said patterned mask to a reduced thickness, wherein said reduced thickness is less than said first thickness;
(d) forming a passivating film over at least exposed vertical portions of said gate conductor layer, said passivating film comprises a C-containing film, a Si-containing film, a Sixe2x80x94C-containing film or combinations thereof; and
(e) etching said gate conductor layer having reduced thickness and said conductor layer protected by said patterned mask to form undercut notches within said gate conductor layer at lower corners of said gate conductor layer that is beneath said patterned mask.